With demands for size reduction and power consumption reduction of electronic apparatuses in recent years, demands for size reduction and power consumption reduction of semiconductor devices included in electronic apparatuses are also increasing. For meeting these demands, semiconductor devices such as power MOS (Metal Oxide Semiconductor) transistors, which are used, for example, in DC-DC converters of electronic apparatuses, need size reduction by adoption of flip-chip structure, and ON-resistance reduction.
This type of semiconductor device generally includes electrodes disposed on a rear surface of a silicon substrate. In the case of the flip-chip structure, however, the rear-surface electrodes need to be disposed on a front surface of the silicon substrate. This structure requires electric connection between a high-concentration layer of the silicon substrate and the front-surface electrodes, and thus produces additional resistance in this electric connecting portion. Accordingly, it is necessary to reduce the resistance of this electric connecting portion.
For example, a manufacturing process of a semiconductor device disclosed in Unexamined Japanese Patent Publication No. 5-29603 for meeting this necessity includes: a step of forming an element separation trench and a substrate contact trench in an SOI (Silicon on Insulator) layer formed on a front surface of a substrate via an insulation film; a step of forming an insulation film within the element separation trench; a step of exposing the substrate through a bottom portion within the substrate contact trench; a step of implanting tungsten in a portion within the substrate contact trench by selective gas phase growth; a step of simultaneously implanting non-doped polysilicon in a remaining portion within the substrate contact trench and within the element separation trench; a step of forming a doped polysilicon film on polysilicon within the substrate contact trench; a step of executing heat treatment for the substrate; and a step of forming substrate electrodes on the doped polysilicon film. These steps realize an electric connection between a support substrate and substrate electrodes by using the tungsten within the substrate contact trench, the non-doped polysilicon containing impurities diffused by the heat treatment, and the SOI layer containing impurities diffused by the heat treatment.